Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
نویسندگان
چکیده
In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, Igate, and subthreshold leakage, Isub. The interaction between Isub and Igate complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the statedependent total leakage current considering the interaction between Isub and Igate. We apply this method to ISCAS benchmark circuits in a projected 100nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.
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تاریخ انتشار 2003